At-speed test using on-chip controller

A circuit is disclosed for testing integrated circuits at functional speed. In one aspect, an on-chip controller is used that accepts event data. The event data identifies a clock sequence to be used to test core logic of an integrated circuit. Multiple source clocks are generated by a phase-lock loop. The clock signals may be at the same frequency, but skewed from each other, or at different frequencies. In any event, the multiple source clocks are supplied to the on-chip controller that uses the source clocks to generate multiple test clocks. The test clocks are used to test the core logic of the integrated circuit at functional speed. In another aspect, external test equipment may supply the source clocks. Additionally, a select signal may choose whether the source clocks are supplied externally to the circuit under test or by the phase lock loop.