Technique for implementing a distributed lock in a processor-based device

A technique for implementing a distributed lock for a shared resource accessible by a plurality of requesters in a processor-based device. The lock is implemented as an array of memory locations, in which the size of each memory location corresponds to a cache line size. Each requester attempting to acquire the lock is assigned a particular memory location at which to wait until lock ownership is available. Acquisition and release of the lock is facilitated by a token-passing scheme.