DUAL LAYER HARD MASK FOR EDRAM GATE ETCH PROCESS

DUAL LAYER HARD MASK FOR EDRAM GATE ETCH PROCESS

A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second ha...

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Bibliographische Detailangaben
Hauptverfasser: Dobuzinsky, David, Khan, Babar, Liu, Joyce, Wensley, Paul, Yu, Chienfan
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.