Semiconductor integrated circuit device having an optimal circuit layout to ensure stabilization of internal source voltages without lowering circuit functions and/or operating performance

In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect lay...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Nakai, Kiyoshi, Riho, Yoshiro, Egawa, Hidekazu, Suzuki, Yukihide, Fujii, Isamu
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!