Semiconductor device array having dense memory cell array and hierarchical bit line scheme
A semiconductor device architecture ( 200 ) is disclosed. Like unit circuits ( 202 ), arranged in rows and columns, are coupled to lower conductive segments ( 204 a - 204 h ). The lower conductive segments ( 204 a - 204 h ) are arranged in an "open" configuration, allowing adjacent unit ci...
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| creator | Ogata, Yoshihiro |
| description | A semiconductor device architecture (
200
) is disclosed. Like unit circuits (
202
), arranged in rows and columns, are coupled to lower conductive segments (
204
a
-
204
h
). The lower conductive segments (
204
a
-
204
h
) are arranged in an "open" configuration, allowing adjacent unit circuits (
202
) be accessed simultaneously. The lower conductive segments (
204
a
-
204
h
) are coupled to higher conductive segments (
208
a
-
208
f
) by reconnector circuits (
210
a
and
210
b
). The higher conductive segments (
208
a
-
208
f
) are arranged into folded pairs (
208
a/
208
d,
208
b/
208
e
and
208
c/
208
f
) between differential-type amplifiers (
212
a
and
212
b
). The reconnector circuits (
210
a
and
210
b
) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (
210
a
and
210
b
) couple adjacent folded higher conductive segment pairs to one another. In a switch configuration, the reconnector circuits (
210
a
and
210
b
) couple a matching lower conductive segment (
204
a
-
204
h
) to each higher conductive segment of the adjacent higher conductive segment pairs. |
| format | Patent |
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200
) is disclosed. Like unit circuits (
202
), arranged in rows and columns, are coupled to lower conductive segments (
204
a
-
204
h
). The lower conductive segments (
204
a
-
204
h
) are arranged in an "open" configuration, allowing adjacent unit circuits (
202
) be accessed simultaneously. The lower conductive segments (
204
a
-
204
h
) are coupled to higher conductive segments (
208
a
-
208
f
) by reconnector circuits (
210
a
and
210
b
). The higher conductive segments (
208
a
-
208
f
) are arranged into folded pairs (
208
a/
208
d,
208
b/
208
e
and
208
c/
208
f
) between differential-type amplifiers (
212
a
and
212
b
). The reconnector circuits (
210
a
and
210
b
) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (
210
a
and
210
b
) couple adjacent folded higher conductive segment pairs to one another. In a switch configuration, the reconnector circuits (
210
a
and
210
b
) couple a matching lower conductive segment (
204
a
-
204
h
) to each higher conductive segment of the adjacent higher conductive segment pairs.</description><language>eng</language><creationdate>2002</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20020031029$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,873,885,64059</link.rule.ids><linktorsrc>$$Uhttps://patentcenter.uspto.gov/applications/09969395$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ogata, Yoshihiro</creatorcontrib><title>Semiconductor device array having dense memory cell array and hierarchical bit line scheme</title><description>A semiconductor device architecture (
200
) is disclosed. Like unit circuits (
202
), arranged in rows and columns, are coupled to lower conductive segments (
204
a
-
204
h
). The lower conductive segments (
204
a
-
204
h
) are arranged in an "open" configuration, allowing adjacent unit circuits (
202
) be accessed simultaneously. The lower conductive segments (
204
a
-
204
h
) are coupled to higher conductive segments (
208
a
-
208
f
) by reconnector circuits (
210
a
and
210
b
). The higher conductive segments (
208
a
-
208
f
) are arranged into folded pairs (
208
a/
208
d,
208
b/
208
e
and
208
c/
208
f
) between differential-type amplifiers (
212
a
and
212
b
). The reconnector circuits (
210
a
and
210
b
) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (
210
a
and
210
b
) couple adjacent folded higher conductive segment pairs to one another. In a switch configuration, the reconnector circuits (
210
a
and
210
b
) couple a matching lower conductive segment (
204
a
-
204
h
) to each higher conductive segment of the adjacent higher conductive segment pairs.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2002</creationdate><recordtype>patent</recordtype><sourceid>EFI</sourceid><recordid>eNqVizELwjAQhbM4iPofbnUQajs5S8VdJ5dyXk9zkFxCkhb6783QPyA8ePC9723N68FeKOg4UQkJRp6FGDAlXMDiLPqtTDODZx_SAsTOrTPqCFY4YSIrhA7eUsCJMmSy7HlvNh90mQ9r78zx1j-v99OUIxbWkgeM0dVrkaB5aJumpjs37aX7x_0Bf9ZB9w</recordid><startdate>20020314</startdate><enddate>20020314</enddate><creator>Ogata, Yoshihiro</creator><scope>EFI</scope></search><sort><creationdate>20020314</creationdate><title>Semiconductor device array having dense memory cell array and hierarchical bit line scheme</title><author>Ogata, Yoshihiro</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_applications_200200310293</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2002</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Ogata, Yoshihiro</creatorcontrib><collection>USPTO Published Applications</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ogata, Yoshihiro</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device array having dense memory cell array and hierarchical bit line scheme</title><date>2002-03-14</date><risdate>2002</risdate><abstract>A semiconductor device architecture (
200
) is disclosed. Like unit circuits (
202
), arranged in rows and columns, are coupled to lower conductive segments (
204
a
-
204
h
). The lower conductive segments (
204
a
-
204
h
) are arranged in an "open" configuration, allowing adjacent unit circuits (
202
) be accessed simultaneously. The lower conductive segments (
204
a
-
204
h
) are coupled to higher conductive segments (
208
a
-
208
f
) by reconnector circuits (
210
a
and
210
b
). The higher conductive segments (
208
a
-
208
f
) are arranged into folded pairs (
208
a/
208
d,
208
b/
208
e
and
208
c/
208
f
) between differential-type amplifiers (
212
a
and
212
b
). The reconnector circuits (
210
a
and
210
b
) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits (
210
a
and
210
b
) couple adjacent folded higher conductive segment pairs to one another. In a switch configuration, the reconnector circuits (
210
a
and
210
b
) couple a matching lower conductive segment (
204
a
-
204
h
) to each higher conductive segment of the adjacent higher conductive segment pairs.</abstract><oa>free_for_read</oa></addata></record> |
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| identifier | |
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| language | eng |
| recordid | cdi_uspatents_applications_20020031029 |
| source | USPTO Published Applications |
| title | Semiconductor device array having dense memory cell array and hierarchical bit line scheme |
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