Semiconductor device array having dense memory cell array and hierarchical bit line scheme

A semiconductor device architecture ( 200 ) is disclosed. Like unit circuits ( 202 ), arranged in rows and columns, are coupled to lower conductive segments ( 204 a - 204 h ). The lower conductive segments ( 204 a - 204 h ) are arranged in an "open" configuration, allowing adjacent unit circuits ( 202 ) be accessed simultaneously. The lower conductive segments ( 204 a - 204 h ) are coupled to higher conductive segments ( 208 a - 208 f ) by reconnector circuits ( 210 a and 210 b ). The higher conductive segments ( 208 a - 208 f ) are arranged into folded pairs ( 208 a/ 208 d, 208 b/ 208 e and 208 c/ 208 f ) between differential-type amplifiers ( 212 a and 212 b ). The reconnector circuits ( 210 a and 210 b ) each have a reconnect configuration and a switch configuration. In a reconnect configuration, the reconnector circuits ( 210 a and 210 b ) couple adjacent folded higher conductive segment pairs to one another. In a switch configuration, the reconnector circuits ( 210 a and 210 b ) couple a matching lower conductive segment ( 204 a - 204 h ) to each higher conductive segment of the adjacent higher conductive segment pairs.