Gate array layout for interconnect

In a gate array having adjacent lines of PFETs and NFETs along a first axis, some gates of PFETs and/or NFETs extend into the region between wells and along a first (x) axis of the lines of transistors to overlap along the axis, so that an extended gate of an nth transistor, a gate of an (n-1)th non-extended transistor and a gate of an (n−1)th non-extended transistor of the opposite polarity lie along an axis (y) perpendicular to the first axis. In a rectangular layout, the upper right transistor (having an extended gate) is connected to the lower left transistor by a short connection along the y axis.