Voltage translator, particularly of the CMOS type

A CMOS voltage translator having a differential cell circuit portion connected between first and second supply voltage references, and including first and second transistor pairs connected together in series between the supply voltage references. A first divider of the first supply voltage reference for producing a first reduced supply voltage reference on a first internal circuit node, and a second divider of the first supply voltage reference for producing a second reduced supply voltage reference on a second internal circuit node is included, as well as a multiplexer circuit portion connected between the first and second reduced supply voltage references to supply first and second reference voltages to the differential cell circuit portion, respectively on third and fourth internal circuit nodes.