Integrated circuit and method of manufacturing same

An integrated circuit arrangement having two NMOS transistors with different cut off voltages and two PMOS transistors with different cut off voltages. Channel regions of the NMOS transistors exhibit the same dopant concentration. The analogous case applies to the PMOS transistors. The different cut off voltages are achieved by different chemical compositions of the gate electrodes of the transistors. Preferably, the chemical compositions of the gate electrodes of respectively one of the NMOS transistors and one of the PMOS transistors thereby coincide. Si 1−x Ge x with 0 x 1 is suitable as a material for the gate electrodes. The transistors preferably form pairs with transistors complementary to one another that exhibit the same cut off voltages. Given a dopant concentration of the channel regions of the NMOS transistors that is approximately 1.5 times greater than a dopant concentration of the channel regions of the PMOS transistors, the value of x amounts, for example, to 0.47 for respectively one of the transistors in each of the pairs or zero for respectively another of the transistors in each of the two pairs.