METHOD FOR FABRICATING A HYBRID ISOLATION STRUCTURE

Alternative methods are provided for fabricating a hybrid isolation structure on a semiconductor substrate, wherein, the hybrid isolation structure includes a shallow trench isolation (STI) and a field oxide isolation formed by local oxidation of silicon (LOCOS). In detail, the STI is formed within a device region that is operated at a low working voltage, a logic device region, to efficiently enhance the device density. On the other hand, the LOCOS isolation is formed within a device region that is operated at a high working voltage, a memory device region, to ensure the reliability and performance of the devices.