Method for contact size control for nand technology

The present invention provides a method for providing an interconnect in a flash memory device. A first embodiment includes forming at least one contact hole in a peripheral area of the device; bombarding a bottom of the at least one contact hole with ions, where the ions break down undesired oxide residing at the bottom of the at least one contact hole; depositing a barrier metal layer into the at least one contact hole, where the barrier metal layer breaks down remaining undesired oxide at the bottom of the at least one contact hole, and where bombarding with the ions and the depositing of the barrier metal layer minimize an undesired widening of the at least one contact hole; and depositing a contact material into the at least one contact hole. With the first embodiment, both the ions and the titanium break down the undesired oxide while neither breaks down the desired oxide at the sides of the contact hole to a significant degree. Thus, the undesired oxide at the bottom of the contact hole is removed while the enlargement of the contact hole is minimized. A second embodiment of the method, a contact hole having tapered sides with a top being wider than a bottom is used, where the tapered sides minimizes chances of inadvertently etching any field oxide adjacent to the contact hole. In a third embodiment of the method, the first and second embodiments are combined, minimizing the enlargement of the contact hole and the chances of inadvertently etching the field oxide simultaneously. The reliability of the device is thus increased.