Design and analysis of high speed capacitive pipeline DACs
Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mV pp ) the DAC performance is s...
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Veröffentlicht in: | Analog integrated circuits and signal processing 2014-09, Vol.80 (3), p.359-374 |
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Hauptverfasser: | , , |
Format: | Artikel |
Sprache: | eng |
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Online-Zugang: | Volltext |
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Zusammenfassung: | Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mV
pp
) the DAC performance is shown to be limited by the clock feed-through and settling effects in the SC array rather than by the capacitor mismatch or kT/C noise, which appear negligible in this application. While it is possible to design a highly linear output driver with HD3 |
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ISSN: | 0925-1030 1573-1979 1573-1979 |
DOI: | 10.1007/s10470-014-0350-9 |