Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation

A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm 2 . Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is -133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.