On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors

Novel architectures for designing modulo 2 n +1 subtractors and combined adders/subtractors are proposed in this manuscript. Both the normal and the diminished-one representations of the operands are considered. Unit gate estimates and CMOS VLSI implementations reveal that the proposed modulo 2 n +1 subtractors for operands in the normal representation are more efficient than those previously proposed. The proposed diminished-one modulo 2 n +1 subtractors have a complexity similar to that of the corresponding diminished-one adders. Modulo 2 n −1 subtractors and adders/subtractors are also considered for the sake of completeness and a comparison between alternative architectures is provided.