Formal Verification: An Essential Toolkit for Modern VLSI Design

Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. Topics include: FV algorithms to gain full coverage without exhaustive simulation; FV tools and how they differ from simulation tools; instant test benches to gain insight into how models work and find initial bugs; learn from Intel insiders sharing their knowledge and solutions to complex design problems. --