Design of a delay efficient carry select adder

The goal of VLSI design is to increase speed while lowering space, power, and delay requirements. One of the key topics of research in VLSI system design is the development of a digital adder with the best possible area and speed. An arithmetic logic unit serves as the fundamental component of micro...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Brindavanam, Gokulavasan, Babu, Disha David, Sundararajan, Durga Devi, Sivasankaran, Harish, Kaleeswaran, Yuvan Sanjay
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Adding circuits Arithmetic and logic units Delay Digital signal processors Mathematical analysis Microprocessors Systems design Very large scale integration
Online-Zugang:	Volltext
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