Design of a delay efficient carry select adder

The goal of VLSI design is to increase speed while lowering space, power, and delay requirements. One of the key topics of research in VLSI system design is the development of a digital adder with the best possible area and speed. An arithmetic logic unit serves as the fundamental component of microprocessors, microcontrollers, and digital signal processors (ALU). The adder design of an ALU determines its performance. The Carry Propagation Delay (CPD), area, and power are crucial parameters for the adder’s structure. The carry choose strategy has been identified as a good cost, performance trade-off in the design of carry propagation adders. However, the conventional carry select adder (CSLA) still takes up a lot of room because of the twin ripple carry adder structure. Numerous authors put up various ideas to lessen the carry select adder’s area, power and delay. In this article, we’ll contrast the solutions and conclusions of those authors.