Implementation of field-programmable Gate array-based clock synchronization in the fiber channel communication system

A sub-nanosecond clock synchronization scheme based on the field programmable gate array (FPGA) is proposed for the Fiber Channel (FC) communication system in this paper. The counter value of the slave node is synchronized to that of the master node through the embedded IEEE 1588 protocol over the communication link. In order to ensure the counter clocks have the same frequency in both nodes, which is recovered from the FC communication link, the clock phase difference is measured by the digital dual mixer time difference technique and the data recovery technique in the Gigabyte Transceiver, and then it is compensated by the mixed-mode clock manager in FPGAs. The proposed clock synchronization approach is evaluated with an FC communication system that has a serial rate of 12.5 Gbps, and the reported experimental results show that the proposed clock synchronization module can achieve a time difference lower than 1 ns.