High speed and area efficient RNS based FIR filter design using distributed arithmetic approach

The finite impulse response filter is a key building component in a wide range of signal processing algorithms. The amount of multiply and accumulate (MAC) operations determines the level of difficulty in VLSI implementation of FIR filters. These activities take up a lot of space, time, and energy. Several methods and filter designs have been evolved to create FIR filters more efficiently to address this problem. To save area and power, the multiplier block in the FIR filter is being replaced with an efficient memory technique called Distributed arithmetic (DA). The precomputed and stored in ROM or Lookup Tables operations on input and filter coefficients are part of this design (LUT). Data and filter coefficients are typically binary. Design time is inversely related to the number of bits in the input data. The architecture’s performance will suffer if the amount of input data is excessive. Rather than using binary numbers, we use RNS (Residue Number System) to divide a large number into many smaller ones, and then perform arithmetic computations on the smaller ones. This reduces both the amount of time spent on the critical path and how quickly the smaller numbers can be converted back to binary numbers using the Chinese remainder theorem.