A modified dynamic comparator for lowering peak kink in differential amplifier and latch

A dynamic comparator usually has two stages; differential amplifier as stage 1 and latch-based circuitry as stage 2. A differential amplifier amplifies the difference in the input, whereas the latch is used for comparison. Based on the comparison, the latch provides logic 0 and logic 1 to its output. In the dynamic comparator, the kinks at the output of the latch and the Differential Amplifier are available. In this research article, a method is introduced to reduce the kinks of the latch and Differential Amplifier. In this article, a multiplexer (using pass transistor logic) is used to reduce kink at the Differential Amplifier output, and an NMOS transistor is used to reduce kink at the latch output. Both the conventional and modified dynamic comparators are simulated in cadence Virtuoso and taken length 180nm and 90nm technology node. We have analyzed different comparator circuits based on delay and power. All this circuitry has a clocking frequency of 500 MHz in both stages of the comparator and assures input common-mode rail-to-rail voltage.