Analysis of power in logic circuits using various clock-gating techniques

In circuit design, in order to reduce the dynamic and clock network power consumption by limiting its activity factor, clock gating strategy is used. By separating the clock from the other circuit block which is not used currently, the clock gating substantially minimizes dynamic power dissipation. In consequence, there are three elements of power consumption: one is power consumed by combinational logic; second one is power consumed by flip-flops; and last one is power consumed by clock tree design. In this case, the clock gating is used to investigate their application. Here, we define the clock gating technique efficacy in logic circuits using simple and pipeline sequential circuits. Because this approach is also to minimize power. Designers utilize the clock gating approach to lower overall dynamic power because it reduces power by shutting off the inactive stage.