Design of 32-bit MAC unit using fast adders and vedic multiplier

MAC (Multiply - Accumulate) Unit is the basic fundamental block of the computing devices, specifically DSP (Digital Signal Processor). Multiplier, Adder and Accumulator are basic consist parts of MAC Unit. In many DSP Applications MAC unit is used in convolution theorem operations, signal filtering etc. And it is also used in Multimedia Image Processing, Image / video processing. LUT’s (Look - Up Tables) and delay shows the performance of MAC. Therefore it is necessary for designing an efficient MAC Unit which is better in area and delay performances. When the number of additions and multiplications are reduced, the delay and area of the MAC also reduced. Vedic Multiplier is used in the proposed study for the design of our MAC. Multiplication using Unit is designed using Vedic technique is the old, easy and fast way for multiplication process. Vedic multiplier is constructed using UTS (Urdhava Thiryagbyam Sutra). To design a 32 Bit MAC Unit we need 16 bit Multipliers that gives output as 32 Bits. Firstly various adders are compared based on their LUT and delay factor. And next Vedic multiplier and booth multiplier are compared and then MAC Unit is designed. All the units have been coded in Verilog. The synthesis and simulation of project is done using ModelSim6.4a software and Xilinx ISE 9.1i.