High efficient accurate DL-PO logic multiplier design for low power applications

The main objective of this research article is to design high efficient accurate DL-PO logic multiplier for low power applications. primarily, the execution of DL-PO Multiplier is based in VLSI chips is used as critical element. In the multiplier, product information are utilised to create the propagator and generator signals in the same way. While designing dual partial product unit, optimized multiplier are used most widely. The DL-PO logic Multiplier uses adequate hardware implementation. The DL-PO logic depends on Multiple selection logic module (MSLM). Hence compared to state-of-the-art system, the DL-PO logic Multiplier systems gives effective results in terms of speed, area and delay.