A low-jitter timing generator based on completely on-chip self-measurement and calibration in a field programmable gate array

This paper presents a high-stability and low-jitter Arbitrary Timing Generator (ATG) design based on the Xilinx Field Programmable Gate Array (FPGA) and its special integrated delay line. In recent years, FPGA-based or application specific integrated circuit-based delay lines have been used to achieve picosecond-level timing resolution. Devices with pure digital delay methods can only acquire triggers at the clock rising edges when triggered externally. Therefore, there is a large time irregularity caused by the uncertainty of the entry time of the trigger, which is difficult to compensate and leads to a large time jitter of outputs. We describe the design of an ATG that includes jitter self-measurement and calibration methods, which is available for both internal and external trigger modes. This structure is completely based on the FPGA’s own resources and has the advantages of being simple and flexible. Experimental results show a sub-nanosecond timing resolution of 78 ± 20 ps with a minimum of 120 ps and a time jitter of 160 ± 20 ps in the external trigger mode after compensation.