The design of low power Sobel edge detection in FPGA

An edge in an image is a boundary or contour at which a significant change occurs in the intensity level. Edge detection is the technique adopted to locate these sharp changes in the images. The proposed work attempts to design a low power Sobel edge detection in FPGA. Initially the basic edge detection circuit is modified with low power adders to reduce the overall power consumption, which is done in software simulation. The pixel values of the image under consideration are fed to Xilinx architecture. A small set of pixels are taken and absolute values are calculated which will be compared to the pre-defined threshold value to obtain edges and non-edges. If the gradient exceeds the threshold value, it will be treated as an edge, else it will be discarded. Finally, the entire pixels of an image are fed into Xilinx via an array and traced the edges and non edges of the image. For the implementation of Sobel edge detction in FPGA, EDGE Spartan 6 is chosen which is an image processing FPGA. For the same, a text file of pixel values is generated with End Of File (EOF) mode. This text of pixels will be transferred to FPGA via UART communication and the sending of data stops once it reaches the EOF. The EDGE Spartan 6 will process all these pixels and the edge detected image is displayed on the VGA.