Multilevel nonvolatile memory effects in hybrid devices containing Cd Se ∕ Zn S nanoparticle double arrays embedded in the C 60 matrices

Electrical properties of nonvolatile memory devices containing core/shell Cd Se ∕ Zn S nanoparticle double arrays embedded in the C 60 layers formed by using a spin-coating technique were investigated. Transmission electron microscopy images showed that Cd Se ∕ Zn S nanoparticles were randomly distributed in the C 60 layers. Capacitance-voltage ( C - V ) measurements on Al ∕ C 60 /double-stacked Cd Se ∕ Zn S nanoparticle arrays/ C 60 ∕ p - Si devices showed that the flat-band voltage shift of the C - V curve related to the charge storage density was enhanced due to a stack of the Cd Se ∕ Zn S nanoparticle layers and that the flat-band voltage shift increased with the magnitude of applied bias voltage due to the variations of the charged electron density in the stacked Cd Se ∕ Zn S nanoparticle double arrays.