Mechanistic understanding of the interfacial properties of metal-PtSe contacts
With the advantages of a moderate band gap, high carrier mobility and good environmental stability, two-dimensional (2D) semiconductors show promising applications in next-generation electronics. However, the accustomed metal-2D semiconductor contact may lead to a strong Fermi level pinning (FLP) ef...
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Veröffentlicht in: | Nanoscale 2023-08, Vol.15 (32), p.13252-13261 |
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Zusammenfassung: | With the advantages of a moderate band gap, high carrier mobility and good environmental stability, two-dimensional (2D) semiconductors show promising applications in next-generation electronics. However, the accustomed metal-2D semiconductor contact may lead to a strong Fermi level pinning (FLP) effect, which severely limits the practical performance of 2D electronics. Herein, the interfacial properties of the contacts between a promising 2D semiconductor, PtSe
2
, and a sequence of metal electrodes are systematically investigated. The strong interfacial interactions formed in all metal-PtSe
2
contacts lead to chemical bonds and a significant interfacial dipole, resulting in a vertical Schottky barrier for Ag, Au, Pd and Pt-based systems and a lateral Schottky barrier for Al, Cu, Sc and Ti-based systems, with a strong FLP effect. Remarkably, the tunneling probability for most metal-PtSe
2
is significantly high and the tunneling-specific resistivity is two orders of magnitude lower than that of the state-of-the-art contacts, demonstrating the high efficiency for electron injection from metals to PtSe
2
. Moreover, the introduction of
h
-BN as a buffer layer leads to a weakened FLP effect (
S
= 0.50) and the transformation into p-type Schottky contact for Pt-PtSe
2
contacts. These results reveal the underlying mechanism of the interfacial properties of metal-PtSe
2
contacts, which is useful for designing advanced 2D semiconductor-based electronics.
Strong interfacial interactions in metal-PtSe
2
contacts lead to a significant interfacial dipole and FLP effect which can be effectively weakened by introducing a buffer layer, providing useful guidelines for designing high-performance 2D electronics. |
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ISSN: | 2040-3364 2040-3372 |
DOI: | 10.1039/d3nr02466k |