Fermi-level depinning of 2D transition metal dichalcogenide transistors

Recently, mainstream silicon (Si)-based materials and complementary metal oxide semiconductor (CMOS) technology have been used in developing extremely tiny sized (of a few nanometers) devices. However, with the reduction of transistor characteristic dimensions, many new challenges such as the short channel effect and high heat dissipation problems have emerged. Two-dimensional transition metal dichalcogenides (2D TMDs) are deemed the most promising semiconductor materials to conquer the challenge of the short channel effect owing to their excellent properties, including high mobility and atomic thickness. Nevertheless, Fermi-level pinning (FLP) occurs when TMDs are in direct contact with metal electrodes, which causes an uncontrollable Schottky barrier and a high contact resistance, limiting the device performance. In this review, we summarize the recent progress on how to circumvent FLP between 2D TMDs semiconductors and metals. Firstly, the related concepts, aiming to get an in-depth understanding of FLP are introduced. Secondly, we discuss the factors contributing to FLP in detail and the strategies of Fermi-level depinning according to these factors. Finally, we present a summary and outlook, which will provide a guideline for suppressing FLP in the process of fabricating high-performance 2D TMD devices. In this review, we summarize the recent progress on how to circumvent FLP between 2D TMD semiconductors and metals.