Negative differential transconductance device with a stepped gate dielectric for multi-valued logic circuits

Multi-valued logic (MVL) technology is a promising approach for improving the data-handling capabilities and decreasing the power consumption of integrated circuits. This is especially attractive as conventional complementary metal-oxide-semiconductor technology is approaching its scaling and power density limits. Here, an ambipolar WSe 2 field-effect transistor with two or more negative-differential-transconductance (NDT) regions in its transfer characteristic (NDTFET) is proposed for MVL applications of various radices. The operation and charge carrier transport mechanism of the NDTFET are studied first by Kelvin probe force microscopy, electrical, and capacitance-voltage measurements. Next, strategies for increasing the number of NDT regions and engineering the NDTFET transfer characteristic are discussed. Finally, the extensibility and tunability of our concept are demonstrated by adapting NDTFETs as core devices for ternary, quaternary, and quinary MVL inverters through simulations, where only WSe 2 is employed as a channel material for all devices comprising the inverters. The MVL inverter operation principle and the mechanism of the multiple logic state formation are analyzed in detail. The proposed concept is practically verified by the fabrication of a ternary inverter. An extensible and tunable concept of WSe 2 -based negative differential transconductance devices for computational multi-valued logic systems of various radices.