Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodesElectronic supplementary information (ESI) available: Details of gold colloid synthesis, device fabrication, and sample characterization; digital photograph of array, RF sputtering optimization results, FESEM cross-sections, AFM height profiles, FESEM image of thick oxide, C-V curve of control sample, and XPS spectra. See DOI:10.1039/c1nr10884k

We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices. Floating gate...

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Hauptverfasser: Muralidharan, Girish, Bhat, Navakanta, Santhanam, Venugopal
Format: Artikel
Sprache:eng
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Zusammenfassung:We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices. Floating gate devices fabricated using 2D arrays of 7 nm gold nanoparticles as charge storage nodes show reproducible memory characteristics.
ISSN:2040-3364
2040-3372
DOI:10.1039/c1nr10884k