Physical synthesis addresses timing-performance issues in complex FPGAs

Physical synthesis addresses timing-performance issues in complex FPGAs

Higher density FPGAs present today's designers with a good-news, bad-news scenario. The good news is that the next-generation FPGAs are in the multimillion-gate range with performance well above 100 MHz, opening a whole set of applications for FPGAs, particularly multimedia- and communications-...

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Veröffentlicht in:EDN 2001-02, Vol.46 (4), p.66-66
1. Verfasser: Garrison, Jeff
Format: Magazinearticle
Sprache:eng
Schlagworte:
Arrays
Design
Design engineering
Designers
Electronics industry
Optimization techniques
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Beschreibung
Zusammenfassung:Higher density FPGAs present today's designers with a good-news, bad-news scenario. The good news is that the next-generation FPGAs are in the multimillion-gate range with performance well above 100 MHz, opening a whole set of applications for FPGAs, particularly multimedia- and communications-based designs with stringent performance and time-to-market requirements. The bad news is that these new devices bring with them some serious design challenges.
ISSN:0012-7515
2163-4084