NVM integration ensures a successful experience

NVM integration ensures a successful experience

* Make sure the NVM's voltage requirements are met. The NVM's specified voltage requirements are those at its input(s). Voltage droop between the SoC power pin and the internal NVM VDD can cause the voltage at the NVM block to be out of spec. Powersequencing requirements may also come into...

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Veröffentlicht in:Electronic Design 2007-05, Vol.55 (11), p.54
1. Verfasser: Morrell, Larry
Format: Magazinearticle
Sprache:eng
Schlagworte:
Circuit design
Consumer electronics
Design
Design and construction
Designers
Electrical design
Embedded systems
Guidelines
Integration
Intellectual property
Memory (Computers)
Methods
Projects
Random access memory
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Zusammenfassung:* Make sure the NVM's voltage requirements are met. The NVM's specified voltage requirements are those at its input(s). Voltage droop between the SoC power pin and the internal NVM VDD can cause the voltage at the NVM block to be out of spec. Powersequencing requirements may also come into play.
ISSN:0013-4872
1944-9550