Design and validation of 0.25 (mu m) integrated circuit yield model

Significant effort has been made to derive credible tool targets for the tool set for the SEMATECH 0.25 micrometer logic process. Besides using real manufacturing data from 0.30 micrometers to 0.50 micrometers process technologies from 3 SEMATECH member companies, tool development experts at SEMATECH have been consulted for feedback on the per wafer pass (PWP) targets based on their exposure to 0.25 micrometer tool projects. The following improvements should be considered to reduce the error of estimation: 1. electrical to process data mapping to obtain kill ratios, 2. use of process zone pareto to drive yield improvement, 3. use critical area extraction software for each mask level instead of using minimum geometries for the full chip area, 4. acquired data at several points along the yield curve to see the effect of clustering with improving yields, and 5. verification of 1/X superscript 3 defect size distribution.