Positive bias temperature instabilities on sub-nanometer EOT FinFETs

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

► PBTI was measured on low EOT triple gated FinFETs with TiN/HfO gate stack to assess their reliability. ► TiN gate reduces SiO interlayer and increases PBTI degradation. ► Wider devices present a higher degradation which may be caused by a higher density of defects on the top-wall. ► PBTI degradati...

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Veröffentlicht in:Microelectronics and reliability 2011-09, Vol.51 (9-11), p.1521-1524
Hauptverfasser: Feijoo, P.C., Cho, M., Togo, M., San Andrés, E., Groeseneken, G.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Charge
Degradation
Density
Devices
Electronics
Exact sciences and technology
Hafnium oxide
Instability
Oxides
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Tin
Transistors
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Beschreibung
Zusammenfassung:► PBTI was measured on low EOT triple gated FinFETs with TiN/HfO gate stack to assess their reliability. ► TiN gate reduces SiO interlayer and increases PBTI degradation. ► Wider devices present a higher degradation which may be caused by a higher density of defects on the top-wall. ► PBTI degradation could be a problem for ultra low EOT for both planar and FinFET devices. PBTI degradation on FinFETs with HfO2/TiN gate stack (EOT
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2011.06.014