A 5-Gbit/s monolithically-integrated low-power clock recovery circuit in 0.18- mu m CMOS

In order to make a 10 Gbit/s 2-1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery (CR) circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator (VCO) is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector (PFD) is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature (PVT) variation. SMC 0.18- mu m CMOS technology is adopted and the core area is 170 mu m x 270 mu m. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of -114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.