New serial architecture for the Berlekamp-Massey algorithm

New serial architecture for the Berlekamp-Massey algorithm

We propose a new efficient serial architecture to implement the Berlekamp-Massey (1968, 1969) algorithm, which is frequently used in BCH and Reed-Solomon (1960) decoders. An inversionless Berlekamp-Massey algorithm is adopted which not only eliminates the finite-field inverter but also introduces ad...

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Veröffentlicht in:IEEE transactions on communications 1999-04, Vol.47 (4), p.481-483
Hauptverfasser: Hsie-Chia Chang, Shung, C.B.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithms
Architecture
Clocks
Computer architecture
Decoders
Decoding
Delay
Equations
Hardware
Inverters
Multipliers
Parallel processing
Polynomials
Scheduling
Scheduling algorithm
Serials
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Beschreibung
Zusammenfassung:We propose a new efficient serial architecture to implement the Berlekamp-Massey (1968, 1969) algorithm, which is frequently used in BCH and Reed-Solomon (1960) decoders. An inversionless Berlekamp-Massey algorithm is adopted which not only eliminates the finite-field inverter but also introduces additional parallelism. We discover a clever scheduling of three finite-field multipliers to implement the algorithm very efficiently. Compared to a previously proposed serial Berlekamp-Massey architecture, our technique significantly reduces the latency.
ISSN:0090-6778
1558-0857
DOI:10.1109/26.764911