Substrate noise-coupling characterization and efficient suppression in CMOS technology

Substrate noise-coupling characterization and efficient suppression in CMOS technology

This brief investigates the substrate noise coupling using S-parameters measurement. Radio frequency domain analysis shows that the noise isolation is strongly dependent on layout geometry, including the parameters such as p-n junction, physical separation distance, guard ring (GR), and deep n-well...

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Veröffentlicht in:IEEE transactions on electron devices 2004-05, Vol.51 (5), p.817-819
Hauptverfasser: Yeh, Wen-Kuan, Chen, Shuo-Mao, Fang, Yean-Kuen
Format: Artikel
Sprache:eng
Schlagworte:
CMOS
CMOS integrated circuits
Devices
Guards
Integrated circuit layout
Integrated circuit noise
Joining
Noise
P-n junctions
Radio frequencies
Scattering parameters
Separation
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Beschreibung
Zusammenfassung:This brief investigates the substrate noise coupling using S-parameters measurement. Radio frequency domain analysis shows that the noise isolation is strongly dependent on layout geometry, including the parameters such as p-n junction, physical separation distance, guard ring (GR), and deep n-well (DNW). We found that the noise coupling can be efficiently diminished by incorporating GR and DNW structures.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2004.825814