A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique

A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique

A 7bit 1.0Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90nm CMOS process technology the ADC consumes 230mW...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEICE transactions on electronics 2010-01, Vol.E93.C (3), p.288-294
Hauptverfasser: Ono, Koichi, Ohkawa, Takeshi, Segami, Masahiro, Hotta, Masao
Format: Artikel
Sprache:jpn
Schlagworte:
Architecture
CMOS
Consumption
Electronics
Folding
High speed
Power consumption
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A 7bit 1.0Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90nm CMOS process technology the ADC consumes 230mW with 1.2V and 2.5V supplies and has a SNR of 38dB.
ISSN:1745-1353
DOI:10.1587/transele.E93.C.288