FPGA-based architecture for real-time data reduction of ultrasound signals

► We define a methodology for automatically real-time ultrasound signal data reduction based on an FPGA architecture. ► The methodology practically enables an ultrasound equipment to acquire non-stop ultrasound signals. ► From several tests we achieved an average of 96.5% data reduction and less than 0.3 mm of thickness error. ► The method is mainly useful in applications where people can not access and where high speed inspections are required. This paper describes a novel method for on-line real-time data reduction of radiofrequency (RF) ultrasound signals. The approach is based on a field programmable gate array (FPGA) system intended mainly for steel thickness measurements. Ultrasound data reduction is desirable when: (1) direct measurements performed by an operator are not accessible; (2) it is required to store a considerable amount of data; (3) the application requires measuring at very high speeds; and (4) the physical space for the embedded hardware is limited. All the aforementioned scenarios can be present in applications such as pipeline inspection where data reduction is traditionally performed on-line using pipeline inspection gauges (PIG). The method proposed in this work consists of identifying and storing in real-time only the time of occurrence (TOO) and the maximum amplitude of each echo present in a given RF ultrasound signal. The method is tested with a dedicated immersion system where a significant data reduction with an average of 96.5% is achieved.