A Two-Step-Recess Process Based on Atomic-Layer Etching for High-Performance [Formula Omitted] p-HEMTs

We investigated 60-nm In@@d0.52@Al@@d0.48@As/In@@d0.53@Ga@@d0.47@As pseudomorphic high-electron mobility transistors (p-HEMTs) fabricated by using a Ne-based atomic-layer-etching (ALET) technology. The ALET process produced a reproducible etch rate of 1.47 Aring/cycle for an InP etch stop layer, an excellent InP etch selectivity of 70 against an In@@d0.52@Al@@d0.48@As barrier layer, and an rms surface-roughness value of 1.37 Aring for the exposed In@@d0.52@Al@@d0.48@As barrier after removing the InP etch stop layer. The application of the ALET technology for the gate recess of 60-nm In@@d0.52@Al@@d0.48@As/In@@d0.53@Ga@@d0.47@As p-HEMTs produced improved device parameters, including transconductance (G@@dM@), cutoff frequencies (f@@dT@) > and electron saturation velocity (vsat) in the channel layer, which is mainly due to the high etch selectivity and low plasma-induced damage to the gate area. The 60-nm In@@d0.52@Al@@d0.48@As/In@@d0.53@Ga@@d0.47@As p-HEMTs fabricated by using the ALET technology exhibited G@@dM@,@@dMax@ = 1-17 S/mm, f@@dT@ = 398 GHz, and v@@dsat@ = 2.5 X 10@@u7@ cm/s.