A 232-Channel Epiretinal Stimulator ASIC
This paper presents the architecture and design of a stimulator ASIC for a visual prosthesis. The circuit employs fully wireless operation and features 232 channels with a maximum of 116 parallel stimulations. The architecture is separated into shared global functions and locally distributed stimula...
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Veröffentlicht in: | IEEE journal of solid-state circuits 2007-12, Vol.42 (12), p.2946-2959 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | This paper presents the architecture and design of a stimulator ASIC for a visual prosthesis. The circuit employs fully wireless operation and features 232 channels with a maximum of 116 parallel stimulations. The architecture is separated into shared global functions and locally distributed stimulation functions. High tissue impedance of epiretinal stimulation sets the need for high-voltage output compliance, which is typically as high as 22.5 V in this implementation. For implantation-ready design, full testability has been achieved, full ESD protection was implemented, and novel safety features were realized in order to combine highly flexible operation with maximum innocuousness for the patient. The overall stimulator occupies 22 mm 2 in a 0.35 HVCMOS technology. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2007.908693 |