A 1.1 GHz 12 [mu]A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A 1.1 GHz 12 [mu]A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential [abstract truncated by publisher].

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Veröffentlicht in:IEEE journal of solid-state circuits 2008-01, Vol.43 (1), p.172-179
Hauptverfasser: Wang, Yih, Ahn, Hong Jo, Bhattacharya, U, Chen, Zhanping, Coan, T, Hamzaoglu, F, Hafez, W M, Jan, Chia-Hong, Kolar, P, Kulkarni, S H, Lin, Jie-Feng, Ng, Yong-Gee, Post, I, Wei, Liqiong, Zhang, Ying, Zhang, K, Bohr, M
Format: Artikel
Sprache:eng
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Zusammenfassung:A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential [abstract truncated by publisher].
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2007.907996