Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies

Substrate noise is a major obstacle for mixed-signal integration. While the power consumption scales linearly with the clock frequency, substrate noise does not have this scaling due to the resonances in the transfer function of the supply current to the substrate. This paper addresses a practical technique to estimate the substrate noise frequency spectrum of a large mixed-mode System-on-Chip (SoC) with multiple supplies and embedded memories. The results have been verified with substrate noise measurements on a 60-MHz 220-Kgates telecom SoC implemented in a 0.35 /spl mu/m CMOS process on an EPI-type substrate. We compute a linear chip-level substrate model together with the single-cycle representation of piecewise-linear noise sources of three supply regions used in this ASIC. Based on this model we accurately estimate the four major resonances in the substrate noise spectrum and their relative magnitudes with 2 dB relative error at the major resonance with respect to measurements. We also present substrate noise measurements at different operating modes of the WLAN receiver. These measurements show that output I/O buffers generate significant substrate noise where an increase of 44% is measured for substrate noise peak-to-peak value due to the additional simultaneous switching of six output I/O buffers with already fully switching datapath and two output I/Os.