A 13.3-Mb/s 0.35-μm CMOS analog turbo decoder IC with a configurable interleaver

Circuits and an IC implementation of a four-state, block length 16, three-metal one-poly 0.35- mu m CMOS analog turbo decoder with a fully programmable interleaver are presented. The IC was tested at 13.3 Mb/s, has a 1.2 mu s latency, and consumes 185 mW on a single 3.3-V power supply, resulting in...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2003-11, Vol.38 (11), p.2010-2015
Hauptverfasser:	Gaudet, V.C., Gulak, P.G.
Format:	Artikel
Sprache:	eng
Schlagworte:	Blocking Circuits CMOS Decoders Energy consumption Integrated circuits Phases Power consumption
Online-Zugang:	Volltext
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