Manufacturing enhancements for CoSi sub(2) self-aligned silicide at the 0.12- mu m CMOS technology node

As integrated circuit manufacturing moves to the 0.12- mu m and finer-line technologies, a more comprehensive understanding of the manufacturability of the cobalt silicide (CoSi sub(2)) module is needed. In this paper, a detailed study of the manufacturability of cobalt self-aligned silicide (Salicide) for the 0.12- mu m and finer technology nodes is discussed. Experimental design for the CoSi sub(2) processing steps included cobalt (Co), titanium (Ti), and titanium nitride (TiN) depositions; the first and second rapid thermal anneals (RTA1 and RTA2) and the selective metal etch. Grain structure (by X-ray diffraction), surface roughness (by atomic force microscopy), sheet resistance, thickness uniformity and leakage current measurements were taken to characterize the SAlicide process module. The results show that by using a TiN rather than Ti capping layer: a) the CoSi sub(2) sheet resistance nonuniformity has been improved; b) the CoSi sub(2) thickness is independent of the capping layer thickness; and c) CoSi sub(2) to silicon interface roughness is reduced, thus reducing junction leakage currents. Anneal studies indicate the RTA1 temperature dominates the CoSi sub(2) grain structure and grain size with higher annealing temperatures resulting in rougher CoSi sub(2) surfaces and higher junction leakage currents.