A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

A 1-Gb/s/pin 512-Mb DDRII SDRAM has been developed using a digital delay-locked loop (DLL) and a slew-rate-controlled output buffer. The digital DLL has a frequency divider for DLL input, performs at an operating frequency of up to 500 MHz at 1.6 V, and provides internal clocking with 50% duty-cycle...

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Veröffentlicht in:IEEE journal of solid-state circuits 2003-05, Vol.38 (5), p.762-768
Hauptverfasser: Matano, T., Takai, Y., Takahashi, T., Sakito, Y., Fujii, I., Takaishi, Y., Fujisawa, H., Kubouchi, S., Narui, S., Arai, K., Morino, M., Nakamura, M., Miyatake, S., Sekiguchi, T., Koyama, K.
Format: Artikel
Sprache:eng
Schlagworte:
Buffers
Chips
Circuit testing
Circuits
Clocks
Delay
Digital
Dynamic link libraries
Electric potential
Frequency conversion
Frequency dividers
Impedance
Low voltage
SDRAM
Timing
Ultra large scale integration
Voltage
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Zusammenfassung:A 1-Gb/s/pin 512-Mb DDRII SDRAM has been developed using a digital delay-locked loop (DLL) and a slew-rate-controlled output buffer. The digital DLL has a frequency divider for DLL input, performs at an operating frequency of up to 500 MHz at 1.6 V, and provides internal clocking with 50% duty-cycle correction. The DLL has a current-mirror-type interpolator, which enables a resolution as high as 14 ps, needs no standby current, and can operate at voltages as low as 0.8 V. The slew-rate impedance-controlled output buffer circuit reduces the output skew from 107 to 10 ps. This SDRAM was tested using a 0.13-/spl mu/m 126.5-mm/sup 2/ 512-Mb chip.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2003.810030