Thermal limitations of InP HBTs in 80- and 160-gb ICs

Bipolar transistor scaling laws indicate that the dissipated power per unit collector-junction area increases in proportion to the square of the transistor bandwidth, increasing to /spl sim/10/sup 6/ W/cm/sup 2/ for InP heterojunction bipolar transistors (HBTs) designed for 160 Gb/s operation. A ver...

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Veröffentlicht in:	IEEE transactions on electron devices 2004-04, Vol.51 (4), p.529-534
Hauptverfasser:	Harrison, I., Dahlstrom, M., Krishnan, S., Griffith, Z., Kim, Y.M., Rodwell, M.J.W.
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer simulation Devices Dissipation Etching Finite element methods Heterojunction bipolar transistors Indium compounds Indium phosphides Integrated circuit modeling Phosphorus compounds Semiconductor devices Thermal resistance
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Zusammenfassung:	Bipolar transistor scaling laws indicate that the dissipated power per unit collector-junction area increases in proportion to the square of the transistor bandwidth, increasing to /spl sim/10/sup 6/ W/cm/sup 2/ for InP heterojunction bipolar transistors (HBTs) designed for 160 Gb/s operation. A verified three-dimensional finite-element thermal model has been used to analyze the thermal resistance of InP in the context of 80 and 160 Gb/sup -1/ integrated circuits. The simulations show that the maximum temperature in the device can be significantly higher than the experimentally determined base-emitter junction temperature. Devices suitable for 160-Gb/s circuits will be thermally possible if the InGaAs etch-stop or contacting layer is removed from the subcollector.
ISSN:	0018-9383 1557-9646
DOI:	10.1109/TED.2004.824686