Scan chain failure analysis using laser voltage imaging

Design-for-test methodologies have enabled considerable reduction in test time and improvement in defect isolation. Defects which impede correct operation of scan chains are a significant fraction of yield loss. Isolating these defects is an important but underserved activity. Image-based technologies examining an extended area of die are popular diagnostics techniques because they provide intuitive and useful results. Emission based microscopy and laser fault isolation techniques, both static and dynamic, are readily available. However, neither technique provides insight to specific timing characteristics of the IC. Photoemission microscopy suffers from decreasing signal strength at lower voltages, and laser techniques can be difficult to perform with production test setups, requiring involved test pattern and setup adaptation. In this paper, we describe two scan chain defect localization case studies using Laser Voltage Imaging [1] on 40 nm bulk CMOS technology operating at 0.9 V. Results are also compared to other diagnostics techniques, including software-based shift analysis and photoemission microscopy.