A low-latency asynchronous shift register

A low-latency asynchronous shift register

In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the des...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2004-05, Vol.51 (5), p.217-221
Hauptverfasser: Chan, R.P.-K., Choy, O.C.-S., Chan, C.-F., Pun, K.-P.
Format: Artikel
Sprache:eng
Schlagworte:
Architecture
Asynchronous circuits
Blocking
Circuit topology
Circuits
Clocks
Delay
Design engineering
Electric potential
Flip-flops
Logic circuits
Shift registers
Switches
Switching circuits
Voltage
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed.
ISSN:1549-7747
1057-7130
1558-3791
DOI:10.1109/TCSII.2004.824051