A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture

A binary backplane transceiver core in 0.13- mu m dual-gate low-voltage (LV) CMOS, operating at 0.6-9.6 Gb/s with an area of 0.56 mm super(2), is presented. The core uses two taps of transmit preemphasis and an adaptive receive equalization strategy incorporating one tap of unrolled decision feedback equalization (DFE), a linear equalizer, and a bandwidth control mechanism integrated with the receiver calibration circuitry. The output driver uses a cascode structure to achieve a 1.7-V peak-to-peak (p-p) differential output swing with low area and minimal overhead power. The core has extensive optional test features including a built-in bit error rate (BER) tester, voltage margining circuit, and an on-chip receiver sampling scope. The power varies from 152 to 275 mW as the speed varies from 6.25 to 9.6 Gb/s while maintaining a voltage margin of 30 mV at a BER of 10 super(-15).